1. Field of the Invention
The present invention relates to a semiconductor device and a test method for manufacturing a semiconductor device, and more particularly to a semiconductor device and test method for manufacturing a semiconductor device which prevent both cracking and peeling of a bonding pad at the time of probing during a chip test.
2. Related Art
In the past, there has been the problem of peeling between a bonding pad and an interlayer insulation film, leading to a reduction in assembly yield.
In order to solve this type of problem, a semiconductor device as shown in FIG. 7 of the accompanying drawings is proposed. The bonding pad of this semiconductor device comprises a plurality of metal interconnect layers and a large number of via holes 61 filled with conductive materials, and a plurality of metal interconnect layers are connected by a large number of holes 61, so as to prevent peeling between the bonding pad 62 and the interlayer insulation film. In the method, however, because of the design restriction of the hole-to-hole spacing, there is a limit to the surface area of holes used to make connection between metal pads. In particular, with an increase in the number of functions built into a chip, the number of pins used to access signal lines increases, this leading to a decrease in the bonding pad surface area. If the bonding pad surface area becomes small, there is an increase in the shock imparted to the bonding pad. Additionally, to prevent an increase of the delay time by interconnects, in the case in which a fluorine-doped silicon oxide film (FSG) is used as a low-dielectric-constant interlayer insulation film, a reaction occurs between the fluorine and the barrier metal, this facilitating peeling at the boundary between the pad and the interlayer insulation film.
For this reason, in the unexamined Japanese patent publication (KOKAI) No.6-196525 there is disclosure of a bonding pad using a plurality of slits filled with conductive materials for connection between an upper metal layer and a lower metal layer, so as to enhance the wire pulling strength at the time of bonding.
Because the above-noted technology makes use of a slits to make connections between an upper metal layer and a lower metal layer, the slit surface area making connection between an upper metal layer and a lower metal layer is larger compared to the case of using holes, so that the strength of the connection made between metal layers is improved, this being somewhat effective in preventing bonding pad peeling.
In the above-noted technology, however, in the case in which when performing a chip test before performing wire bonding, if the intrusion direction of the probe is perpendicular to the direction of the slit, there are cases in which cracks occur between the side walls of the slit and the interlayer insulation film. In such cases, when performing bonding of the assembly, because a crack has already occurred, there is a tendency toward pad peeling.
Additionally, in the case of a structure in which an interconnect is provided beneath a bonding pad, if a crack formed at the time of chip testing reaches the interconnect provided beneath a bonding pad, because there is an area which is not surrounded with an interlayer film around the interconnect, there is a deterioration of immunity to migration in this part of the interconnect. In the case in which water intrudes from the crack part, there was the problem of corrosion of the interconnect, with the possibility of an open connection in the interconnect.
Accordingly, it is an object of the present invention to improve on the above-noted drawbacks in the prior art, by providing a novel semiconductor device and test method for manufacturing a semiconductor device, which prevent cracking and peeling of a bonding pad and prevent open connections caused by corrosion.
To achieve the above-noted objects, the present invention adopts the following basic technical constitution.
Specifically, the first aspect of the present invention is a semiconductor device in which a bonding pad thereof comprises a first interconnect layer and a second interconnect layer, the bonding pad comprising: a plurality of slit-shaped trenches arranged parallel to each other and formed within an interlayer insulation film provided between the first and second interconnect layers, a first connection part 151 provided within one of the slit-shaped trenches and connecting the first interconnect layer and the second interconnect layer, a second connection part 152 and a third connection part 153 provided within other slit-shaped trenches and connecting the first interconnect layer and the second interconnect layer, respectively, the second connection part 152 and the third connection part 153 being disposed so as to sandwich the first connection part 151 with a prescribed spacing B, a first bridge connecting part 161 and a second bridge connecting part 162, formed in the interlayer insulation film, connecting the first connection part 151 and the second connection part 152, and a third bridge connecting part 163, formed in the interlayer insulation film, connecting the first connection part 151 and the third connection part 153, the third bridge connecting part 163 being disposed between the first bridge connecting part 161 and the second bridge connecting part 162.
In the second aspect of the present invention, a width of a connecting portion of the connection part making connection to the bridge connecting part is narrower than that of the connection part.
In the third aspect of the present invention, a width of a connecting portion of the bridge connecting part making connection to the connection part is narrower than that of the bridge connecting part.
The fourth aspect of the present invention is a test method for a semiconductor device in which a bonding pad thereof comprises a first interconnect layer and a second interconnect layer, the bonding pad comprising; a plurality of slit-shaped trenches arranged parallel to each other and formed within an interlayer insulation film provided between the first and second interconnect layers, a first connection part provided within one of the slit-shaped trenches and connecting the first interconnect layer and the second interconnect layer, a second connection part and a third connection part provided within other slit-shaped trenches and connecting the first interconnect layer and the second interconnect layer, respectively, the second connection part and the third connection part being disposed so as to sandwich the first connection part with a prescribed spacing, a first bridge connecting part and a second bridge connecting part, formed in the interlayer insulation film, connecting the first connection part and the second connection part, and a third bridge connecting part, formed in the interlayer insulation film, connecting the first connection part and the third connection part, the third bridge connecting part being disposed between the first bridge connecting part and the second bridge connecting part, wherein the method comprising; contacting a test probe for testing the semiconductor device with the bonding pads so as to be in a direction parallel to a longitudinal direction of the connection part.
The fifth aspect of the present invention is a test method for a semiconductor device in which a bonding pad 2 thereof comprises a first interconnect layer 14 and a second interconnect layer 17, the bonding pad 2 comprising a plurality of connection parts 15, provided within a plurality of slit-shaped trenches 15xe2x80x2 formed in an interlayer insulation film 16, respectively, and connecting the first interconnect layer 14 and the second interconnect layer 17, the connection parts 1 being disposed in one direction with a prescribed spacing, wherein the method comprising; contacting a test probe 3 for testing the semiconductor device with the bonding pads 2 so as to be in a direction H2 parallel to a longitudinal direction H1 of the connection part 1.
FIG. 1 of the accompanying drawings is a plan view of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view thereof. As shown in these drawings, the upper-layer metal pad 17 formed by the uppermost interconnected layer and the lower-layer metal pad 14 formed by the lowermost interconnect layer are connected by a connection part 15 provided on the interlayer insulation film 16.
The longitudinal direction of the connection part 15 is disposed so as to be parallel to the direction in which the probe makes contact during a chip test. By adopting this configuration, because the connection part 15 is disposed so as to be parallel to the direction of force from the probe 19 when the probe comes into contact with the metal pad 17 during a chip test, it is difficult for cracks to occur.
Therefore, during a chip test, because it is difficult for cracks to occur in the bonding pad, it is difficult for pad peeling to occur at the time of assembly, thereby improving the assembly yield.